2) I'm guessing that what your typical ADC does is integrate the PDM signal until the next word clock edge comes along, at which point it places the sum in a shift register and begins to clock it out.
For an ADAT slave device with ADCs that output a PDM signal, I suppose what you need to do is similar. You'd use a PLL to derive your oversampling clock from the word clock, and integrate PDM bits until a word clock comes along.