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1. clacke (clacke@social.heldscal.la)'s status on Friday, 04-May-2018 04:26:14 EDT clacke
   Never heard of https://en.wikipedia.org/wiki/Parallax_Propeller before.
   
   > multi-core processor parallel computer architecture microcontroller chip with eight 32-bit reduced instruction set computer (RISC) central processing unit (CPU) cores
   
   > Parallax Inc., released all of the Propeller 1 P8X32A hardware and tools as open-source hardware and software under the GNU General Public License (GPL) 3.0. This included the Verilog code, top-level hardware description language (HDL) files, Spin interpreter, PropellerIDE and SimpleIDE programming tools, and compilers.
   
   > There are at least six different versions of Forth, both commercial and open-source software, available for the Propeller.
   
   > As of 2014, Parallax is building a new Propeller with cogs that each will run at about 200 MIPS, whereas the current Propeller's cogs each run at around 20 MIPS. The improved performance would result from a maximum clock speed increase to 200 MHz (from 80 MHz) and an architecture that pipelines instructions, executing an average of nearly one instruction per clock cycle (approximately a ten-fold increase).
   
   Anyone play with this thing? Anyone know what the current status is on the upgrade?
   1. clacke (clacke@social.heldscal.la)'s status on Friday, 04-May-2018 04:30:25 EDT clacke

      in reply to
      > Parallax endeavors to supply Propellers as long as we have demand (i.e., foreseeable future, a minimum 20 to 25 years). As an example of our commitment, Parallax still manufactures the BASIC Stamp I and it was designed over 20 years ago.
      
      Nice.
      
      https://www.parallax.com/product/p8x32a-d40
      1. clacke (clacke@social.heldscal.la)'s status on Friday, 04-May-2018 04:34:33 EDT clacke

         in reply to
         Apparently the Propeller II, Propeller 2 or P2 is a thing, but not yet in ASIC form:
         
         https://forums.parallax.com/categories/propeller-2-multicore-microcontroller
         
         People are posting about things they are doing with FPGA implementations.
         1. clacke (clacke@social.heldscal.la)'s status on Friday, 04-May-2018 04:36:39 EDT clacke

            in reply to
            Also, P2 is not open hardware.
            
            > I think we will open-source the design, but probably not for a few years.
            
            https://forums.parallax.com/discussion/168368/is-p2-open-source-and-business-considerations
            1. clacke (clacke@social.heldscal.la)'s status on Friday, 04-May-2018 04:47:12 EDT clacke

               in reply to
               Here's another nice rabbit hole, long discussion of the merits of RISC-V vs P2, and a link to a size-optimized RISC-V 32 implementation:
               
               https://forums.parallax.com/discussion/166409/risc-v
               
               https://github.com/cliffordwolf/picorv32