Conversation

Made excellent progress on my #Kestrel3 SIA core's receiver logic last night. It is formally verified to be correct, so I'm hoping I can find the time tonight to wrap the SIA core all together and implement local loopback logic. This will probably take all evening.

Then, hoping tomorrow evening, I can implement the Verilator code to drive the SIA core from the processor's point of view and verify in simulation that the core as a whole works.

Then, the SIA will be done done.