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  1. wohali 💯 (wohali@octodon.social)'s status on Thursday, 10-Oct-2019 18:28:51 EDT wohali 💯 wohali 💯

    @libc usually net[7:0] for Verilog notation or net[7 downto 0] in VHDL.

    Verilog is the more common syntax and you'll see this type of notation on schematics more often in my experience.

    In conversation Thursday, 10-Oct-2019 18:28:51 EDT from octodon.social permalink
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