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  1. Vertigo (vertigo@mastodon.social)'s status on Tuesday, 12-Dec-2017 11:57:07 EST Vertigo Vertigo

    Achievement unlocked!! https://pastebin.ca/3947098

    This is my very first FPGA core written in the Chisel 3 DSL. This is a remake of the Kestrel-2's GPIA general purpose interface adapter.

    The GPIA-2:
    - is Wishbone 1.4 Pipeline compliant.
    - fixes the GPIA bug where byte writes corrupts the opposing byte of the output port.

    In conversation Tuesday, 12-Dec-2017 11:57:07 EST from mastodon.social permalink
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