Notices by Vertigo (vertigo@mastodon.social), page 20

@h Kestrel-3.

Since my current CPU lacks any MMU, the kernel would not support "safe" binaries. It'd be shared-memory, single address space, just like Kickstart 1.3.

*After* I build the MMU for it (OR, after I switch the CPU out for a Rocket core), then I can upgrade the kernel to add support for "safe" binaries and implement the new system calls needed to make communicable regions of memory.

@h When you think about it, IBM's System/360 was just like the Amiga when it was first introduced: a shared, single address space environment. They had 2KB quasi-pages which prevented one task from writing into another task's memory, but *nothing* stopped tasks from *reading* other tasks memory. Today, z/OS is fully memory protected.

So, somehow, there must be a way to evolve an AmigaOS-like environment without breaking compatibility.

@h I don't think it was lack of vision; it was the vision of putting computers in the hands of untrained masses that drove the interfaces we have today. There inlies the problem: untrained.

The untrained masses became either complacent, or worse, actively reveled in their ignorance. This is literally their point of view: "Why should I learn how to type these god-awful cryptic gobbledygook when I can just drag and drop these pretty pictures? Reading is hard! Let's go shopping!"

@elomatreb @djsundog Wait until it starts talking back to you with a Lisp.

(Sorry, the door was open; I had to walk through it.)

Yeesss!!! I got pictured numeric output working!!

https://chiselapp.com/user/kc5tja/repository/kestrel-2dx/fdiff?v1=0be4e70044df0941&v2=73281fff570be96e&sbs=1

@rysiek @banjofox @vfrmedia @varx @djsundog http://bulletjournal.com

@djsundog @feld RISC-V currently inherits much of Alpha's design philosophy, and seems to be the natural heir to Alpha's throne.

Whenever you hear of RISC-V code running in "M-Mode" or "Machine Mode", that's our version of PALcode, for instance. ;)

I was feeling down/depressed as I normally do at work these days. This song brought a tear to my eye, as it seems most Camel songs do these days.

https://www.youtube.com/watch?v=CdpbiscUpB8&index=3&list=PL3_RdUGxg2XmeirqbP9HBLte4ehw4f7cE

I wish I could give everyone in Camel a hug for music like this. Totally gets me through the day.

@jjg @clacke I feel the need to stand on a soap-box here. :)

We need to remember that RISC-V is an instruction set architecture. It's a specification, and therefore, has nothing to say about whether or not instructions are speculatively executed, in what order they're executed (within reason, of course), etc.

Specific implementations may or may not be affected. KCP53000, my own RV64I CPU, is not affected. Reports today confirm neither are cores built around Rocket. BOOM remains uncertain.

@aeonofdiscord @djsundog These types of attacks are known to work inside of Javascript sandboxes (apparently, at least), so I fully expect malignant ads to be one of the first, easily exploitable vectors for these exploits. Make sure you use a quality ad-blocker would be at the top of my list of defenses.

@clacke I'm just reading the Google Project Zero page and as well https://meltdownattack.com/ .

@clacke However, Spectre still works inside a completely user-space program (e.g., Javascript breaching its sandbox to read browser internal state). This is still a hardware-level bug that should not happen, and it's caused by the interaction between the memory hierarchy; this is actually not CPU specific (AMD, Intel, ARM, and most likely, RISC-V) all would/could suffer from it. It's caused by speculation leaving breadcrumbs of sorts in the cache controllers off-core.

@clacke A hardware-level fix for this would double the burden on the MMU, which would slow the instruction execution rate appreciably. This is the problem with super-long pipelines, and why you should never have a CPU with a pipeline longer than, say, 10 stages. And that's being generous; I *actually* can't see any reason for anything longer than 6.

@beadsland @djsundog There was a time in my life when I'd oppose this vociferously. Today, I'm in total agreement.

I still use the term "software engineer" here in the bay area because it sells well. But, I now loathe it. I don't want to be a software engineer anymore. I just want to be a programmer. I'm happy with just "programmer."

@beadsland @djsundog I really think that we should return to an apprenticeship model for bringing up new software engineers and architects.

@gdkar @djsundog On IBM mainframes, you have an instruction called SIE, which stands for Start Interpreted Execution. This lets the processor nest virtual machines pretty much indefinitely with minimal impact to performance.

It works almost exactly like a call to Unix select(), where when SIE returns, you get not only the current state of the VM, but also what caused the instruction to "return."

SIE doesn't need to be in supervisor state to run.

We can learn a lot from mainframes.

@satchmoz BOOM architecture would be the most likely candidate, as I believe it makes use of speculative execution (it's a superscalar processor with branch prediction). But, I'm not sure.

I'm almost certain that the Rocket core and designs derived from it will not employ speculative instruction execution, so at least for these cores, RISC-V would have a high probability of being immune from Spectre-class attacks.

@vfrmedia @gdkar @djsundog You can still get 65816 chips in DIP package at 14MHz (under-rated; they usually can reach 20MHz without any heatsinking) speeds.